1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory having memory cells with multiple charge traps, more particularly to a method of programming data into the memory cells.
2. Description of the Related Art
A known type of semiconductor nonvolatile memory has memory cells with two charge traps, each of which can store bi-level data (‘0’ or ‘1’), enabling the memory cell to store two bits of data. One such semiconductor nonvolatile memory, described in Japanese Patent Application Publication (JP) No. 2005-64295, places two physically discontinuous charge traps comprising silicon nitride films on the source and drain sides of the gate electrode of each memory cell. FIG. 1 conceptually illustrates four memory cells in this type of memory. The silicon nitride films are indicated by hatching. The initial state of a charge trap, with no trapped charge, represents ‘1’. The programmed state, with electrons trapped in the silicon nitride film, represents ‘0’.
A semiconductor nonvolatile memory with this structure is programmed, read, and erased as follows.
To program a charge trap that is in the initial ‘1’ state and thereby write a ‘0’ into the charge trap, if the charge trap is located on the drain side of the memory cell, positive voltages are applied to the drain and gate electrodes of the memory cell and the source electrode is held at the ground potential. Hot electrons are thereby injected into the charge trap, and the stored data value changes to ‘0’.
To read the information stored on the drain side of the memory cell, positive voltages are applied to its source and gate electrodes and the drain electrode is held at the ground potential. The memory cell then conducts current, but if the drain charge trap has been programmed to the ‘0’ state, the current flow is considerably reduced as compared with the initial ‘1’ state. A relatively high current is accordingly read as a ‘1’ and a relatively low current is read as a ‘0’.
To erase a charge trap that has been programmed to the ‘0’ state by returning it to the initial ‘1’ state, a positive voltage is applied to the adjacent source or drain electrode, a zero or negative voltage is applied to the gate electrode, and the opposite drain or source electrode is left open (floating). This generates hot holes in the drain region. The hot holes are injected into the charge trap, where they neutralize the trapped charge, erasing the stored information. Information can also be erased by heat treatment or exposure to ultraviolet light.
Since information is read by discriminating between high and low current values, ideally ‘0’ should be represented by the same current value in all memory cells, and likewise ‘1’ should be represented by the same current value in all memory cells. In practice, however, process variations and other factors produce cell-to-cell differences in the current values.
FIG. 2 schematically shows a histogram of the currents obtained by reading data from one side of a large number of memory cells when the other side (the mirror side) is in the initial state. The horizontal axis represents the read current value, and the vertical axis represents the number of charge traps producing that current value. The actual current values representing ‘0’ and ‘1’ are distributed around the ideal values. The space between the ‘0’ and ‘1’ current value distributions is referred to as the current window. To read ‘0’ and ‘1’ data correctly, an adequately wide current window is essential.
Work is now proceeding toward enabling this type of memory to store four bits of data per memory cell by distinguishing among four current levels (representing ‘00’, ‘01’, ‘10’, and ‘11’), so that two bits can be stored in each charge trap. One such memory, in which the silicon nitride layer film is formed as a continuous film below the gate electrode, was described by Eitan et al. at the International Electron Devices Meeting (IEDM) of the Institute of Electrical and Electronics Engineers (IEEE) in Washington, D.C. in 2005.
In this four-bit-per-cell memory, a two-phase programming method is used. To prevent cross talk between the two charge traps in a memory cell, both phases are carried out in a series of steps in which the two charge traps are programmed alternately and the programming voltage is gradually raised. Following each step, the programming result is verified by testing the threshold voltage of the memory cell. The first phase is a high-speed phase in which the drain voltage is raised (drain stepping). In the procedure shown in FIG. 4 of a paper published by Eitan et al. in the 2005 IEDM Technical Digest, the initial drain voltage is three volts (3 V) and drain stepping halts when a desired threshold voltage is attained. The second phase is a high-accuracy phase in which the gate voltage is raised (gate stepping). In FIG. 4 of the above paper, gate stepping begins at 7 V and halts when another desired threshold voltage is attained.
Proceeding in this way in a series of program-verify steps enables the desired amount of charge to be injected into the charge trap more accurately than would be possible by injecting the charge in a single step.
In connection with a semiconductor nonvolatile memory such as a flash memory of the floating-gate type that stores multiple bits per memory cell by storing different amounts of charge in the floating gate, JP 10-27486 describes a program-verify procedure that proceeds in order from the memory cells requiring the most programming to those that require the least programming. The purpose of this strategy is to avoid the ‘word-line disturb’ problem, in which the application of high negative voltages to a word line to program selected memory cells on the word line also slightly programs non-selected memory cells on the same word line, disturbing the data stored in the non-selected cells.
The cross-talk problem that occurs in memory cells with two charge traps is similar: programming the charge trap on one side of the cell may reduce the read current value of the charge trap on the mirror side. For example, if memory cells of the type described in JP 2005-64295 are used to store two bits of information as shown in FIG. 1, and if the charge trap on the source side is programmed to the ‘0’ state while the charge trap on the drain side is left in the ‘1’ state, an unwanted reduction in the read current of the charge trap on the drain side may occur. The main reason is that the charge stored in the source-side charge trap somewhat impedes the flow of current through the memory cell when the drain-side charge trap is read.
FIG. 3 schematically illustrates this problem. The horizontal axis indicates the read current value and the vertical axis indicates histogram frequency as in FIG. 2. The solid curves indicate the histograms of bits programmed to ‘0’ and ‘1’ in a large number of memory cells in which the mirror bit is in the ‘1’ state. The dotted curve indicates the position to which the ‘1’ histogram is shifted by programming the mirror bit to ‘0’. Although the ‘0’ and ‘1’ data are still distinguishable, the current window is considerably narrowed. An accurate program-verify procedure can overcome this problem by reducing the spread of the read current values in the ‘1’ and ‘1’ histograms, thereby assuring that a reasonable current window is maintained.
A similar problem also occurs if the memory cell is used to store more than two bits of information. Suppose, for example, that the semiconductor nonvolatile memory described in JP 2005-64295 is adapted to store four bits per cell as shown in FIG. 4, by programming four levels of charge, representing ‘00’, ‘01’, ‘10’, and ‘11’, into the charge traps. FIG. 5 schematically shows histograms of the read currents obtained from a large number of memory cells in this type of semiconductor nonvolatile memory; the horizontal axis represents current values and the vertical axis represents histogram frequencies of the read current values for charge traps storing ‘00’, ‘01’, ‘10’, and ‘11’ data when the mirror charge trap is in the initial (‘11’) state. The current windows are smaller than when only two bits are stored per memory cell. The dotted lines in FIG. 6 indicate the shifts in these histogram curves caused by programming the charge trap on the mirror side of each memory cell to ‘00’. The current windows are now inadequate for reliable reading. In particular, there is now substantially no current window between the ‘11’ distribution when the mirror charge trap is programmed to ‘00’ (the rightmost dotted curve) and the ‘10’ distribution when the mirror charge trap is left in the non-programmed state (the second solid curve from the right).
The strategy proposed in the IEDM paper cited above attempts to overcome this problem by simultaneous (that is, alternate) programming of both sides of the memory cell. When the same data value is programmed into both sides of the memory cell, for example, if the two sides are programmed alternately in a series of steps, the programming procedure can be stopped when both sides have attained substantially the intended read current level.
A problem with this strategy is that when different data values are programmed into the two sides of the memory cell, one side may attain its intended read current before the mirror side does so. Consequently, the number of programming repetitions on the two sides of the memory differs, and programming of one side of the memory cell must continue after programming of the mirror side ends. The continued programming on the one side of the memory cell then affects the read current value on the mirror side. This problem is hard to avoid, especially if the initial programming voltage is the same on both sides of the memory cell, as in the two-phase programming procedure described in the IEDM paper cited above.